1. Field of the Invention
This invention relates to an operating method of a multi-level memory cell.
2. Description of Related Art
Among various memory products, non-volatile memory has been widely applied to personal computers and various consumer electronic devices since it can be written and erased many times and the written data can be retained when the power is off.
The floating gate and the control gate of an electrically erasable programmable read-only memory (EEPROM) are made of doped polysilicon. Since the floating gate is made of conductive doped polysilicon which allows injected electrons or holes to be delocalized, each memory cell in such a memory device has data states “1” and “0” only, i.e., stores only one bit of data.
Conventionally, a floating gate made of polysilicon may be replaced by a charge trapping layer. Generally, the charge-trapping layer is made of silicon nitride and silicon oxide layers are respectively disposed on and under the charge-trapping layer, so that an oxide-nitride-oxide (ONO) composite layer is formed. Such a device is called a silicon/oxide/nitride/oxide/silicon (SONOS) device. Due to the trapping effect of silicon nitride, electrons injected into the charge-rapping layer are localized in certain regions thereof. In a typical SONOS memory cell, two bits can be respectively stored in two portions of the silicon nitride layer respectively close to the drain and the source. However, when one bit has been stored in the portion of the silicon nitride layer close to the drain, a second bit effect will be produced when reverse reading is performed, and thus the silicon nitride layer has to be wide enough to avoid the second bit effect. As a result, neither the size nor the fabrication cost of the memory device can be reduced.